In increasing the data throughput rate for bussed systems, such as processors, memories, personal computers and computer systems, the use of low signal level data transmission busses has been proposed. By reducing the high output voltage level standard for a particular bus, the switching time is improved because the voltage swing from a high output level to a low output level is limited to a few hundred millivolts, as opposed to the older bus standards which required as much as 5 volts of swing to transition from a high voltage state to a low voltage state. The Futurebus standard, for example, has a reduced high level output voltage, a tight specification requirement on the slew rate of the output devices, and a tight specification requirement of the skew, that is the difference between the low-to-high delay. Also, the output drivers are required not to pull the bus below a certain defined low output level voltage, so that the voltage swing is required to be between two tightly defined high and low voltage levels. The bus specification also requires that the output devices be open-collector or open-drain types, that is the bus is pulled up to the high output state by an external R-C network. The output drivers must then overcome these pullup circuits to assert a low voltage level on the bus.
The problem in implementing low voltage level signal busses like the Futurebus using the circuits of the prior art is that switching noise produced by the output driving devices can cause erroneous results in the signal receiving devices. The noise problem is worse for these busses than for older bus standards because the available noise margins have been greatly reduced. If the device driving the bus switches quickly from a high state, that is letting the bus rise to a defined high output level, to a low state, that is outputting a signal of approximately zero volts, ringing may occur on the bus. This ringing can cause the receiving devices to erroneously input a transient as true data, that is the ring can look like a zero state on the bus followed by a high state, then a second zero state. The ringing is caused because the transition from the high state to the low state by the output driver is happening too sharply. This problem is often stated as a slew rate of the output driver device which is too fast.
Further, prior art circuits which address the slew rate problem often only affect it in one direction, that is the slew rate is lowered for the falling edge, for example, but the rising edge is unaffected. This has the effect of increasing the skew rate, the difference between rising and falling transition times, and thus takes the device further away from the bus requirements.
FIG. 1 depicts an exemplary prior art circuit for driving a Futurebus interface. Output buffer 1 is a BiCMOS output driver which includes an input IN for receiving the data to be transmitted on the bus, an inverter 3 for driving the output driving transistor 9, typically an open collector bipolar transistor, as shown here, a base resistor 5 coupled between the inverter 3 and the output driving transistor, and an N channel transistor 7 for feeding the current at the output node into the base of the bipolar transistor 9.
In operation, the circuit of FIG. 1 drives the bus represented by resistor 11 and impedance 13 as follows. Assume initially that the bus is at the high output voltage defined for the Futurebus, e.g. 2.1 Volts, which translates to a high input voltage at the IN terminal. Now assume the IN terminal sees a transition to a low logic level. The inverter 3 responds by outputting a logic one to the base of output transistor 9 and to the gate of N channel transistor 7. As current flows into the base resistor 5, the bipolar transistor 9 moves out of cutoff to a conductive state, so that the collector coupled to the output terminal begins conducting current into the collector, out through the emitter and to ground. Since the output terminal is at a high voltage of 2.1 Volts, the N channel transistor 7 begins taking additional current through its conductive path into the base of bipolar transistor 9, helping to rapidly discharge the output terminal and to provide additional base current to bipolar transistor 9.
When the input terminal IN transitions back to a high logic level, the inverter 3 will output a low logic level voltage and the N channel transistor 7 will cut off. Also the base of bipolar transistor 9 will now be at a low voltage and bipolar transistor 9 will cutoff. The output terminal OUT will then rise to the voltage provided by external pullup resistor 11.
The prior art circuit of FIG. 1 has several problems. There is minimal control of the slew rate of the output terminal. The slew rate of the circuit of FIG. 1 will primarily be determined by the bipolar output driving transistor 9, which will probably be too fast and create transients at the output terminal. Also, the low output voltage will fall to a level of a voltage which is a Vbe drop above ground plus a minimal voltage across the N channel device, which will be lower than is specified for Futurebus applications. Because the rise time of the signal at the OUT terminal is controlled only by the external resistor and load, there is also no skew control, that is there is no relationship between the fall time for the output voltage at the OUT terminal from a high to low output voltage and the rise time from a low to high output voltage.
The proposed high speed bus standards like the Futurebus require output driving circuitry that has a fast transition time and a tightly controlled slew rate and skew, so that switching noise does not exceed the reduced noise margins. In addition, the Futurebus standard requires control of the low output voltage level. The prior art circuitry cannot provide a solution that meets the requirements of these proposed busses. A need for a circuit having fast switching speed and improved slew rate, skew and low output voltage control with low noise characteristics thus exists.